Sr. Physical Design Engineer - Full Chip, Hardware Compute Group

$143,300 - $247,600/Yr

Amazon - Sunnyvale, CA

Full-time - Senior

Sunnyvale, CA

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About the position

The Sr. Physical Design Engineer position at Amazon's Hardware Compute Group is a pivotal role that focuses on the development and innovation of cutting-edge silicon IP, particularly in the context of machine learning accelerators at the edge. This position is part of Amazon Lab126, a team known for its groundbreaking work on products like the Kindle and Echo. The successful candidate will be instrumental in enhancing the performance and efficiency of System on Chips (SoCs) through collaboration with various teams, including architecture, timing, and logic design. In this role, the engineer will engage in a variety of tasks that include I/O planning, bump and redistribution layer (RDL) planning, hard IP integration, and partitioning. The engineer will also be responsible for pin and feedthrough planning, repeater insertion, and power grid generation. A significant aspect of the job involves ensuring that the design is optimized for testability, which includes bus routing and sequential pipeline planning. The engineer will drive improvements in the overall physical design methodology, focusing on floorplan optimization to enhance utilization, quality of results (QoR), runtime, and timing closure. Additionally, the engineer will oversee the coordination of collateral handoffs between the physical design team and other backend design functions, such as clocking and power delivery. The role also includes supervising and mentoring junior engineers, ensuring that the team maintains high standards of quality and efficiency in their work. This position offers a unique opportunity to contribute to the future of technology at Amazon, where innovation and customer satisfaction are at the forefront of the mission.

Responsibilities

• Collaborate with architecture, timing, and logic design teams to deliver cutting-edge and low power SoCs.
• Perform I/O, bump, and RDL planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, and power grid generation.
• Conduct special interface and interconnect planning, bus routing, sequential pipeline planning, and top-level design for testability (DFT).
• Drive efficiency and quality improvements to the overall FC methodology, including floorplan optimization for better utilization, QoR, runtime, and timing and physical aware feedthrough/pin placement.
• Coordinate collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery, and Partition synthesis/APR.
• Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
• Supervise and mentor other engineers.

Requirements

• Bachelor's degree or higher in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS).
• 10+ years of practical semiconductor implementation experience.
• Scripting experience with Perl, Python, Tcl, and shell to automate flows.
• Proficiency in chip front-end and back-end implementation tools such as Fusion Compiler, Design Compiler, ICC2 or Innovus, Primetime, and Tempus.
• Strong communication and analytical skills.
• Ability to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

Nice-to-haves

• MS/PhD in Computer Science, Electrical Engineering, or related field.
• Experience with memory compiler.
• Experience with formal equivalence tools such as Cadence Conformal or Synopsys Formality.
• In-depth knowledge of the entire design process from design specification, defining architecture, micro-architecture, RTL design, and functional verification.
• Experience with DFT and DFM flows.

Benefits

• Comprehensive medical, financial, and other benefits package.
• Equity and sign-on payments as part of total compensation package.
• Access to employee benefits information on Amazon's workplace site.