Sr. Post Silicon Validation Engineer

Cornelis Networks - Chesterbrook, PA

Full-time - Mid Level

Chesterbrook, PA

Professional, Scientific, and Technical Services

About the position

Cornelis Networks is hiring a talented Post Silicon Validation Engineer with extensive experience in SERDES electrical validation. The validation engineer will be involved in all aspects of post silicon validation, including validation of the high-speed interfaces, from ASIC power-on through volume production. The role supports the development of cutting-edge ASICs for deployment in high performance computing (HPC) and artificial intelligent (AI) infrastructures around the world. The engineer will develop post-silicon validation plans and test methodologies to validate performance and functionality of ASICs, including assessment of operating margins of high-speed SerDes across PVT and environmental conditions.

Responsibilities

• Support development of cutting-edge ASICs for deployment in high performance computing (HPC) and artificial intelligent (AI) infrastructures around the world.
• Develop post-silicon validation plans and test methodologies to validate performance and functionality of ASICs, including assessment of operating margins of high-speed SerDes across PVT and environmental conditions.
• Lead bring-up, validation and characterization of high-speed SerDes blocks of ASICs, perform electrical characterization tests and system level link stress tests to ensure the required specifications are met.
• Run tests, review results, debug silicon under test, and create test reports.
• Support debug and resolution of high-speed PHY related failures.
• Support evaluation of new SerDes IP from the IP providers, perform tests to assess compliance with performance requirements and logical and electrical compatibility with legacy devices.

Requirements

• Bachelor's degree in electrical engineering, computer engineering or computer science.
• 5+ years of experience working on SerDes hardware and platforms.
• Detail-oriented and analytical.
• Excellent communicator and collaborator.
• Proactive and solution oriented.
• Team Player.

Nice-to-haves

• Good understanding of Analog/ADC based high speed serial links and equalization techniques.
• Knowledgeable in SerDes PHY building blocks: PLL, CDR, VGA, CTLE, FFE, DFE.
• Experienced in ASIC signal integrity and power integrity design and verification techniques.
• Strong understanding of power management, physical design concepts.
• Expertise in high-speed oscilloscopes, BERTs, AWG, Spectrum Analyzers, and Network Analyzers.
• Proficiency in Python and C programming for hardware testing.
• Experience with silicon bring-up, debug and performance optimization.
• Working knowledge of SerDes Signal Integrity eye diagrams, SNDR, bathtub curves, etc.