Sr. Silicon Learning Engineer
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About The Position
As a Sr. Silicon Learning Engineer at Samsung, you will play a crucial role in maximizing power, performance, and area (PPA) for Samsung's premium mobile GPU. This position is situated within the Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), where we are dedicated to building a center of excellence for Intellectual Property (IP) applied to high-performance computing devices. Your expertise in silicon learning will be instrumental in bridging the power and performance gaps between silicon and design, while continually enhancing our physical design and signoff methodologies. This role offers high cross-functional visibility across the Samsung Semiconductor business, making it vital for the success of our projects. In this position, you will collaborate with various stakeholders across the company to foster synergy between our R&D lab and the Foundry. You will establish strong partnerships with teams in Korea to analyze key product-level test data that captures GPU power and frequency, along with silicon process parameters. As a domain expert, you will analyze silicon test data to correlate metrics such as operating frequency, Vmin, and power with respect to static timing analysis (STA) and power signoff flows. Your ability to identify areas of miscorrelation will be essential, as you will work with other teams to define additional diagnostic collateral, including functional, scan, and memory test patterns. You will also engage with the SARC functional debug and enablement team to conduct focused board-level lab experiments aimed at diagnosing areas of miscorrelation. This includes utilizing special test modes to isolate silicon critical paths. Your problem-solving skills will be put to the test as you identify root causes of issues and communicate specific reasons for miscorrelation, while also helping to define future improvements in design signoff and implementation. With an innovative mindset, you will partner with physical design, DFT, RTL, and architecture teams to define new test features that will enhance our silicon correlation for future designs. We value an inclusive working environment and encourage collaboration with individuals and groups of diverse styles, abilities, and motivations. You will have the opportunity to work with our teams in Korea on silicon diagnostic techniques such as scan diagnostics, LADA, transistor nanoprobing, and physical analysis. This position is ideal for someone who is ambitious about mastering their technical craft through continuous learning and working on cutting-edge technology in a dynamic, fast-paced global environment.
