Sr. Silicon Learning Engineer
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About The Position
Samsung, a world leader in advanced semiconductor technology, is dedicated to the endless pursuit of excellence, aiming to create a better world for all. At the Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are establishing a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices, including mobile and automotive sectors, which are utilized by millions globally. As a Sr. Silicon Learning Engineer, you will play a crucial role in maximizing Power, Performance, and Area (PPA) for Samsung's premium mobile GPU by focusing on silicon learning. This position is vital and offers high visibility across the Samsung Semiconductor business, requiring strong technical skills to bridge the power/performance gaps between silicon and design, while continually enhancing our physical design and signoff methodologies. In this role, you will collaborate with various stakeholders across the company to foster synergy between our R&D lab and the Foundry. You will build strong partnerships with our teams in Korea to understand key product-level test data that captures GPU power and frequency alongside silicon process parameters. As a domain expert, you will analyze silicon test data to correlate metrics such as operating frequency, Vmin, and power concerning Static Timing Analysis (STA) and power signoff flows. Your expertise will be essential in identifying areas of miscorrelation and working with other teams to define additional diagnostic collateral, including functional, scan, and memory test patterns. You will also engage with the SARC functional debug and enablement team on focused board-level lab experiments to diagnose miscorrelation areas, utilizing special test modes to isolate silicon critical paths. Your problem-solving skills will be crucial in identifying root causes of issues and communicating specific reasons for miscorrelation, while also helping to define future improvements in design signoff and implementation. With an innovative mindset, you will partner with physical design, DFT, RTL, and architecture teams to define new test features that will enhance our silicon correlation for future designs. This position requires an open-minded approach to collaboration with diverse teams and individuals, as well as a commitment to continuous learning and mastery of your technical craft in a dynamic, fast-paced global environment.
