Sr. SOC Design Engineer - STA, Hardware Compute Group

$143,300 - $247,600/Yr

Amazon - San Diego, CA

Full-time - Senior

San Diego, CA

10,001+ employees

Sporting Goods, Hobby, Musical Instrument, Book, and Miscellaneous Retailers

About the position

The Sr. SOC Design Engineer - STA role at Amazon involves leading the design and implementation of signoff methodologies for complex semiconductor systems. This position is crucial for ensuring the performance and reliability of the latest generation of machine learning accelerators used in Amazon's Echo devices. The engineer will collaborate with various teams to address design challenges and streamline timing analysis methodologies, contributing to the innovative work at Amazon Lab126.

Responsibilities

• Define and develop signoff methodology and corresponding implementation solution.
• Conduct flow for STA, Crosstalk Delay, and Crosstalk Noise analysis for digital ASIC/SoCs.
• Develop full chip timing constraints and perform full chip/Sub-System STA and Signoff for complex, multi-clock, multi-voltage SoCs.
• Streamline timing signoff criteria, timing analysis methodologies, and flows.
• Analyze and incorporate advanced timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
• Collaborate with Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route, and other teams to address design challenges in timing sign-off.
• Perform concepts of CRPR, clock paths analysis, and tweaks to meet timing.
• Conduct Multi Corner and Multimode analysis.
• Close timing at Signoff corners covering all modes, delay corners for cells and interconnects.

Requirements

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of practical semiconductor implementation experience.
• Scripting experience with Perl, Python, Tcl, and shell to automate flows.
• Proficiency in chip front-end and back-end implementation tools such as Fusion Compiler, Design Compiler, ICC2 or Innovus, and Primetime, Tempus.
• Strong communication and analytical skills.
• Ability to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

Nice-to-haves

• PhD in Computer Science, Electrical Engineering, or related field.
• Experience with memory compiler.
• Experience with formal equivalence tools like Cadence Conformal/Synopsys Formality.
• In-depth knowledge of the entire design process from specification to functional verification.
• Experience with DFT and DFM flows.

Benefits

• Competitive salary and total compensation package including equity and sign-on payments.
• Comprehensive medical, financial, and other benefits.
• Opportunities for professional development and career growth.