Amazon - Sunnyvale, CA
posted about 2 months ago
The Sr. SOC Design Engineer position at Amazon's Hardware Compute Group is a pivotal role that focuses on the design and implementation of advanced silicon IP for machine learning accelerators at the edge. This position is part of Amazon Lab126, a team known for its innovative contributions to products like the Kindle and Echo. The successful candidate will be responsible for defining and developing signoff methodologies and implementation solutions that ensure the performance and reliability of complex digital ASICs and SoCs. In this role, you will engage in full chip timing constraints development, performing static timing analysis (STA) and signoff for multi-clock, multi-voltage systems on chips. You will streamline timing signoff criteria and methodologies, incorporating advanced techniques such as AOCV and POCV based STA, as well as IR Drop aware STA into the overall timing signoff flow. Collaboration is key, as you will work closely with various teams including Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, and IP owners to address design challenges related to timing sign-off. The position also requires a deep understanding of clock path analysis and the ability to perform multi-corner and multi-mode analysis to ensure timing closure at signoff corners. This role is critical in ensuring that the designs meet the stringent performance requirements necessary for the next generation of Amazon's innovative products.