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About the position
The rapid acceleration of deep learning and generative AI is leading to new generations of high-performance and low-power chip architecture. At Ambarella, architecture engineers work at the forefront of this technological leap in computer architecture. Our team members translate algorithms into hardware design specifications, identify performance bottlenecks, optimize system performance and build our knowledge into software libraries to benefit other internal teams and external customers across different target markets. We are looking for a senior architecture engineers who are familiar with the concept of HW/SW co-design, with hands-on hardware modeling experience and critical software expertise to contribute to the next generation of our SOCs.
Responsibilities
- Define architecture specifications for our next generation AI chips.
- Develop functional and performance model for AI accelerator.
- Develop AI compiler that builds AI models into hardware-compatible executables.
- Optimize popular AI models on our platform, evaluate performance efficiency and identify performance bottlenecks.
- Maintain architecture document and other technical writings.
Requirements
- Master or PhD in Computer Science or Electrical Engineering or related field.
- 3-5 year's related experience
- Strong programming skills in C/C++, Python and CUDA knowledge is a plus.
- Deep knowledge of object-oriented programming and software design pattern.
- Deep knowledge of computer architecture and digital circuit design and verification.
- Knowledge of deep learning algorithms especially generative AI is a plus.
- Experience in porting deep learning algorithms to embedded systems and optimizing code for such platforms is a plus.
- Highly motivated and inspired by our AI mission.
