Staff Digital Engineer

$173,200 - $259,800/Yr

Northrop Grumman - Baltimore, MD

Full-time - Senior

Baltimore, MD

Computer and Electronic Product Manufacturing

About the position

The Staff Digital Engineer (FPGA Design) at Northrop Grumman is responsible for designing and developing digital logic designs using modern design methods and tools. This role involves collaboration with design engineers and cross-functional teams to create innovative solutions in FPGA product development. The position requires a strong background in electrical or computer engineering and the ability to work on complex projects that impact global security.

Responsibilities

• Work closely with design engineers utilizing knowledge of modern design methods, tools, and techniques.
• Design, develop, create, and modify digital logic designs implemented with Xilinx and MicroChip FPGAs.
• Execute full FPGA design flow including RTL development, simulation, synthesis, place and route, constraints development, timing analysis, and optimization techniques.
• Collaborate across multi-functional teams to develop innovative solutions.

Requirements

• Bachelor's degree with 12 years of experience, a Master's degree with 10 years of experience, or a PhD with 7 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields. 4 additional years of experience may be considered in lieu of a degree.
• U.S Citizenship is required.
• An active DoD Secret Security Clearance is required with the ability to obtain Special Program Access (SAP) prior to start.
• Experience with industry standard FPGA design implementation tools for IP integration, PnR, CDC such as Xilinx Vivado, Intel Quartus, and QuestaSim.
• Working knowledge of full product life cycle (requirements, design, implementation, and test) of FPGA Design and/or ASIC Design.
• Knowledge of System Verilog, Verilog and/or VHDL.

Nice-to-haves

• Advanced Degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.
• Active DoD Top Secret Clearance or higher.
• Experience with STA constraints generation and timing closure.
• Experience with MATLAB, Mentor Graphics design tools or similar tools.
• Experience in a technical lead role.
• Familiarity with Xilinx and Intel FPGA technology and their supporting tools (i.e. Xilinx Vivado and Intel Quartus).

Benefits

• Medical, Dental & Vision coverage
• 401k
• Educational Assistance
• Life Insurance
• Employee Assistance Programs & Work/Life Solutions
• Paid Time Off
• Health & Wellness Resources
• Employee Discounts