GreenWave Radios - San Jose, CA

posted 18 days ago

Full-time - Senior
San Jose, CA
51-100 employees

About the position

As a Staff Engineer in SoC Design/Integration & Synthesis at GreenWave Radios, you will play a crucial role in enhancing physical design EDA tools and processes for digital design flows. This position involves working with advanced CMOS technology nodes to deliver high-performance SoC designs, collaborating closely with a multi-site team of engineers to ensure production-quality designs for wireless communications in cellular infrastructure.

Responsibilities

  • Develop custom EDA tool enhancements using scripting
  • Provide frontline support for the design team for debugging and developing productivity enhancements
  • Maintain, install, and upgrade existing CAD tools
  • Configure and install foundry PDKs
  • Proactively drive and resolve tool bugs
  • Interact with tool vendors to drive tool fixes and flow improvements
  • Perform tool evaluations of new vendor tools and functions
  • Assist in tape out process, including DRC, LVS, and ERC verification flows
  • Work with the RTL and System design teams to drive the physical design of the device in the early design cycle
  • Design, implement, and verify suitable methodology that meets the QoR goals
  • Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution
  • Deliver physical design of entire SoC, complete with specification, flow, and automation
  • Interface with the RTL design team to drive design modifications to resolve physical design issues and implement ECOs
  • Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality

Requirements

  • BSEE and a minimum of ten years of back-end physical design experience required
  • Deep knowledge of PNR/Synthesis tools, flows and methodologies
  • Hands-on experience with scripting and software development tools (Python, Tcl, C++)
  • Highly capable in Linux/Unix operating systems
  • Working knowledge of IC management revision control - GIT
  • Understanding of SCAN ATPG, MBIST, Logic BIST, DFT/DFM, and fault coverage analysis
  • Proven knowledge of System Verilog/UVM methodology and other advanced design verification techniques
  • Experience with DRC/LVS and extraction flow and rules decks
  • Familiarity with compute server grid systems and server load balancing solutions
  • Familiarity with job monitoring and related software workload tracking tools
  • Excellent MS Office skills, Excel, Word, and PowerPoint, including VBA, Python scripting
  • Excellent verbal and written communication skills
  • Team player with a passion for quality and a strong sense of urgency and pride in their work

Nice-to-haves

  • Expert in Cadence Innovus, Genus, Tempus, and Voltus environments
  • Deep experience in Cadence Virtuoso Design Framework, including flow automation with various EDA tools and PDKs

Benefits

  • Comprehensive group health plan
  • Matching 401(k)
  • Training reimbursement
  • Various paid leaves (vacation, sick leave, holidays, maternity/paternity leave, jury duty)
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