Timing Constraint Engineer

Valtix - San Jose, CA

Full-time - Senior

San Jose, CA

Publishing Industries

About the position

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. CHG silicon chips, optical modules, and full hardware systems solve for a range of demanding use cases from access points for a medium size business, to an enterprise data center, and the largest of hyperscale AI workloads. We are team passionate about technology, have aspirational goals, and love to win as a team. You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips.

Responsibilities

• Developing timing constraints at block, sub-chip, and full-chip levels in multiple timing modes.
• Performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs and checking timing for unconstrained endpoints, no clock, etc.
• Resolving design and flow issues and driving execution to ensure progress and accuracy.
• Participating in SDC validation, CDC delay check, and SDC flow development.
• Developing methodologies, guidelines, and checklists to streamline STA work, along with advising the Physical Design team on best practices.

Requirements

• Bachelor's degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience.
• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.
• Proficient in one or more of the following languages Perl, TCL, Python, Makefile, or other related scripting languages.

Nice-to-haves

• Master's Degree in electrical or computer engineering (or other equivalent field).
• Thorough understanding of Liberty file formats including standard cells/memory/IO/IP modeling and its usage in the ASIC flow.
• Prior experience with SDC debugging tools: Synopsys GCA/TCM, Cadence CCD.
• Strong communications skill and team player.

Benefits

• Quality medical, dental and vision insurance
• 401(k) plan with a Cisco matching contribution
• Short and long-term disability coverage
• Basic life insurance
• Numerous wellbeing offerings
• Up to twelve paid holidays per calendar year
• Floating holiday
• Day off for birthday
• Vacation time off
• Sick time off
• Paid time away to deal with critical or emergency issues
• Additional paid time to volunteer and give back to the community