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The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. CHG silicon chips, optical modules, and full hardware systems solve for a range of demanding use cases from access points for a medium size business, to an enterprise data center, and the largest of hyperscale AI workloads. We are team passionate about technology, have aspirational goals, and love to win as a team. You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips.
