WFO Application Engineer Intern

Cadence Design Systems - San Jose, CA

Full-time - Intern

San Jose, CA

Professional, Scientific, and Technical Services

About the position

As a WFO Application Engineer Intern at Cadence, you will be immersed in a dynamic and innovative environment focused on silicon design and design automation. This internship is designed for students currently enrolled in a STEM or Electrical/Computer Engineering program, providing an exciting opportunity to work with best-in-class Electronic Design Automation (EDA) tools. You will collaborate with technical experts and support the sales team, gaining insights into how a leading company like Cadence operates and how technical teams tackle complex problems in the field of silicon technology. The internship program spans three months and is cohort-based, allowing you to connect with other interns from across the United States. Throughout this period, you will receive hands-on training in various applications used for Digital Design/Simulation, Physical Design, Mixed-signal and Analog Layout, and Advanced Verification. You will learn from experienced professionals, including technical experts, sales executives, and application engineers, who provide design services, technical sales, and customer support to Cadence's advanced customers. During the internship, you will be responsible for completing a design project that utilizes Cadence applications for the design, analysis, and implementation of digital and analog blocks according to specific specifications. This will involve participating in design reviews and sharing your learnings with your cohort and technical management. The program will also cover essential topics such as fundamentals in design, verification, hardware description languages (HDLs), synthesis, timing, embedded software development, and hardware/software co-design and co-verification. You will gain experience in UNIX, C/C++, and scripting languages like Perl, TCL, and Python, as well as digital physical design and implementation, sign-off for timing, IR drop, power analysis, and signal integrity analysis. Additionally, you will have the opportunity to network and engage in fun activities with fellow interns and recent college graduates at Cadence.

Responsibilities

• Participate in a cohort-based internship program with hands-on training in EDA applications.
• Complete a design project using Cadence applications for digital and analog design.
• Engage in design reviews and share learnings with peers and technical management.
• Learn fundamentals in design, verification, HDLs, synthesis, and timing.
• Gain experience in embedded software development and hardware/software co-design.
• Utilize UNIX, C/C++, and scripting languages such as Perl, TCL, and Python.
• Work on digital physical design and implementation tasks.
• Conduct sign-off for timing, IR drop, power analysis, and signal integrity analysis.

Requirements

• Currently enrolled in a STEM or Electrical/Computer Engineering program.
• Basic understanding of digital design and simulation concepts.
• Familiarity with hardware description languages (HDLs).
• Knowledge of UNIX and programming languages such as C/C++, Perl, TCL, and Python.

Nice-to-haves

• Experience with embedded software development.
• Familiarity with design verification processes.
• Interest in silicon design and design automation.

Benefits

• Hands-on training in advanced EDA tools.
• Networking opportunities with other interns and recent graduates.
• Participation in fun activities and events organized for interns.